Design and implementation of a 100 MHz centralized instruction window for a superscalar microprocessor
نویسندگان
چکیده
The maxim of the superscalar architecture is that higher performance can be achieved by executing multiple instructions simultaneously. This can be realized in hardware by using a centralized instruction window. We present the design and implementation of a centralized instruction window capable of out-of-order issue and completion of four instructions per cycle. A compact layout (6.4mm by 2.2mm) of a 32-entry instruction window resulted from a full-custom design in 1.0 m (drawn) 3-layer metal CMOS technology. The layout was veriied by simulation and shown to operate at a clock frequency over 100 MHz.
منابع مشابه
Design and Implementation of a MHz Centralized Instruction Window for a Superscalar Microprocessor
The maxim of the superscalar architecture is that higher performance can be achieved by executing mul tiple instructions simultaneously This can be realized in hardware by using a centralized instruction window We present the design and implementation of a cen tralized instruction window capable of out of order is sue and completion of four instructions per cycle A compact layout mm by mm of a ...
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